1. Field of the Invention
The present invention relates to a process of forming a multilayer conduction wiring of a highly integrated semiconductor device, and more particularly, to a process of forming self-aligned contact holes to form contacts for connecting upper and lower conduction wirings to each other in a highly integrated semiconductor device.
2. Description of the Prior Art
Recently, highly integrated semiconductor devices have had a greater increase in integration degree. Due to such a trend, the area occupied by elements constituting a semiconductor device has sharply reduced. As a result, the tolerance in masking and etching steps involved in fabricating semiconductor device is more limited. Such a limiting tolerance results in a very high aspect ratio and a very small diameter of the contacts which is electrically adopted to the upper and lower conduction wiring layers, disposed over and beneath an intermediate conduction layer, respectively. Where an insulating layer coated over the intermediate conduction wiring layer is selectively etched to form holes for the contacts, the intermediate conduction layer may be partially exposed when masks used for the intermediate conduction wiring and the contact holes are misaligned. To prevent such an exposure of the intermediate conduction layer, a barrier layer is formed over the intermediate conduction wiring layer.
Since the barrier layer is formed by an etching process using a mask, poor contact holes may be formed when the mask used for the barrier layer is misaligned from the mask used for the contacts. This problem will now be described in detail, in conjunction with FIG. 1.
FIG. 1 is a sectional view of a semiconductor device having contact holes formed in accordance with a conventional contact hole forming process. FIG. 1 shows the lower conduction layer 1. Disposed over the lower conduction layer 1 are: a first insulating layer 2, a conduction wiring layer 4, a second insulating layer 5, a barrier pattern 6 and a third insulating layer 8. The barrier pattern 6 is created by the formation of a barrier material layer made of polysilicon to a predetermined thickness over the second insulating layer 5 and then by patterning the barrier material layer by the mask etching process. The barrier pattern 6 overlaps the entire side wall of the conduction wiring 4 and a portion of the upper surface of the first insulating layer 2. To form contact holes 10 through which the lower conduction layer 1 is selectively exposed, the third insulating layer 8, the second insulating layer 5 and the first insulating layer 2, are selectively removed by the use of an etching process utilizing masks as contacts. The contact holes 10 are formed in a self-aligned manner by the barrier pattern 6 so that they have a smaller area than that of the contact regions predetermined by the contact mask.
FIG. 2 is a sectional view of a semiconductor device having poor contact holes formed in accordance with the conventional method shown in FIG. 1. Such poor contact holes result from a misalignment between the mask of the barrier layer and the mask of the contact holes. In FIG. 2, the mask for the barrier layer is shown as being misaligned to the right side. Because of this misalignment of the mask of the barrier layer, the barrier layer pattern 6 is disposed as being shifted to the right side. As a result, the contact holes 10, formed by etching the third insulating layer 8, the second insulating layer 5 and the first insulating layer 2, have a very small area due to the misalignment of the contact mask in the left side, thereby causing the contacts to be abnormally formed.